Scaling Transaction Processing
The InfiniSVM transaction processing architecture is designed for high throughput and low-latency execution. It employs a multi-stage pipeline that optimizes transaction verification, execution, and state updates using parallel processing, RDMA, and FPGA acceleration.
Transaction Processing Pipeline
Each transaction follows a structured pipeline to ensure efficient execution and consistency:
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Ingress & Verification
- Transactions enter the network via an initial ingress point.
- Signature verification (sigverify) and local deduplication are performed to filter redundant transactions.
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Pre-Execution
- Transactions undergo pre-execution to determine their state dependencies.
- Intermediate transaction effects and snapshots are sent to the sequencer via InfiniBand for efficient state tracking.
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Sequencer & Execution Path Selection
- The sequencer, utilizing an SDN switch and FPGA acceleration, determines execution paths:
- Simple Path: If all accounts involved are at their latest state, the transaction bypasses additional validation.
- Complex Path: If at least one account has a newer version, the transaction enters a local mempool for ordering and re-execution.
- The sequencer, utilizing an SDN switch and FPGA acceleration, determines execution paths:
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Parallel Execution & State Updates
- RDMA applies state changes directly for simple path transactions, leveraging a local cache on the SDN switch.
- Complex path transactions are scheduled in the local mempool, ensuring fairness and optimal parallel execution.
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Finalization & Propagation
- Once execution is complete and state changes are committed, the transaction is broadcast globally through a Proof of Propagation (PoPs) network.
Optimized Scheduling & State Storage
To achieve sub-millisecond processing speeds, the sequencer:
- Implements an optimized scheduling algorithm to parallelize dependent transactions.
- Stores account data in a distributed database, ensuring scalability and data integrity.
The InfiniSVM architecture integrates SDN, RDMA, and FPGA-accelerated sequencing to enable high-performance transaction processing. By intelligently routing transactions through simple or complex paths, it minimizes latency while maximizing parallel execution efficiency.
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